1. Field of the Invention
This invention relates to a semiconductor device including a SOI (silicon-on-insulator) substrate on which circuit elements isolated by insulating regions are formed.
2. Description of the Prior Art
Japanese published unexamined patent application 61-59852 discloses a semiconductor device having circuit elements isolated by insulating regions. In Japanese application 61-59852, an insulating film constituting a lower insulating film is formed on a substrate, and a semiconductor layer is superposed on the lower insulating film. The semiconductor layer is divided into element regions between which side insulating regions are formed. The side insulating regions extend vertically from a surface of the semiconductor layer to the lower insulating film. Accordingly, the element regions are completely isolated from each other by the side insulting regions and the lower insulating film. Circuit elements such as transistors are formed in the element regions respectively.
In the semiconductor device of Japanese application 61-59852, noise caused by, for example, a voltage change, tends to be propagated between neighboring circuit elements. The propagation of noise sometimes results in wrong operation of a circuit composed of the elements in the semiconductor device. The lower insulating film and the side insulating regions cause capacitive couplings between neighboring circuit elements. The propagation of noise is enabled by such capacitive couplings.
U.S. Pat. No. 5,241,210 discloses a semiconductor device having elements isolated by insulating regions. In U.S. Pat. No. 5,241,210, an oxide film constituting a lower insulating film is formed on a substrate, and a semiconductor layer is superposed on the lower insulating film. The semiconductor layer is divided into element regions between which side oxide films are formed. The side oxide films extend vertically from a surface of the semiconductor layer to the lower insulating film. Accordingly, the element regions are completely isolated from each other by the side oxide films and the lower insulating film.
Japanese published unexamined utility model application 55-52851 corresponding to Canadian Patent 1017875 discloses a semiconductor integrated circuit having a substrate on which semiconductor element island regions are formed. Circuit elements such as thyristors are provided in the semiconductor element island regions respectively. In Japanese application 55-52851, the semiconductor element island regions are isolated by dielectric films. The substrate has low-resistivity regions made of polycrystalline silicon containing impurity at a high concentration. The low-resistivity regions extend below the dielectric films, so that the semiconductor element island regions are separated from the low-resistivity regions by the dielectric films. The low-resistivity regions also extend between the semiconductor element island regions. To remove capacitive couplings between neighboring semiconductor element island regions, the low-resistivity regions are grounded via an electrode provided on the substrate.
U.S. Pat. No. 4,963,505 discloses a semiconductor device having a lower insulating film formed on a substrate. In the semiconductor device of U.S. Pat. No. 4,963,505, a semiconductor element region extending above the lower insulating film is isolated from adjacent semiconductor element regions by separation regions including side insulating films.
Japanese published unexamined patent application 4-154147 discloses a semiconductor device in which an N epitaxial layer is formed on an N-type Si substrate having a resistivity of 3-10 .OMEGA.cm. In the semiconductor device of Japanese application 4-154147, a semiconductor element region extending above the N epitaxial layer is isolated from adjacent semiconductor element regions by lower and side insulating films. Furthermore, electric shielding layers composed of polycrystalline Si films are provided between the semiconductor element regions. A given potential can be applied to the electric shielding layers via electrodes provided on a top of the semiconductor device.
Japanese published unexamined patent application 3-276747 discloses a lead frame in which islands have projections forming stitches. A Vcc potential and a ground potential can be applied via the stitches and internal leads to a semiconductor chip provided on the islands.
JOURNAL OF NIPPONDENSO TECHNICAL DISCLOSURE, published on Mar. 15 in 1994, discloses a semiconductor device in which semiconductor element regions provided on a silicon substrate are isolated from each other by lower and side insulting films. The substrate includes an N.sup.+ region subjected to a ground potential.
Japanese published unexamined patent application 4-186746 discloses a semiconductor device in which semiconductor element regions provided on a silicon substrate are Isolated from each other by lower and side insulting films. The substrate includes a laminate of an N.sup.+ layer and an N.sup.- layer extending below the semiconductor element regions. The N.sup.+ layer has a resistivity of 10.sup.-4 -10.sup.-2 .OMEGA.cm. The N.sup.- layer has a resistivity of 1-10 .OMEGA.cm.
Japanese published unexamined patent application 5-55100 discloses first and second silicon wafers bonded to form a silicon substrate. The first silicon wafer has an impurity concentration of 1.times.10.sup.14 -1.times.10.sup.18 cm.sup.-3. The second silicon wafer has an impurity concentration of 1.times.10.sup.18 cm.sup.-3 or higher.
Japanese published unexamined patent application 5-144930 discloses a semiconductor device in which semiconductor element regions provided on a p-type silicon substrate are isolated from each other by lower and side insulting films. The substrate has an impurity concentration of about 1.times.10.sup.16 cm.sup.-3.